`include "Header.svh"

module Delay_line #(
    parameter integer LEN = 8
    )(
    input logic             clk             ,
    input logic             rst_n           ,
    input logic             data_in_valid   ,
    input logic             psum_en_di      ,
    input pack_data         data_in [7:0]   ,
    input idx_t             position_di     ,
    output pack_data        data_out[7:0]   ,
    output logic            data_out_valid  ,
    output idx_t            position_do     ,
    output logic            psum_en_do      
    );  
    
    generate
        if (LEN == 0) begin : no_delay
            assign data_out = data_in;
            assign data_out_valid = data_in_valid;
            assign position_do = position_di;
            assign psum_en_do = psum_en_di;
        end
        else begin : with_delay
            pack_data data_reg [0:LEN-1][7:0];
            logic valid_reg [0:LEN-1];
            idx_t position_reg [0:LEN-1];
            integer i;
            logic psum_reg [0:LEN-1];
            always @(posedge clk or negedge rst_n) begin
                if (!rst_n) begin
                    for (i = 0; i < LEN; i = i + 1) begin
                      for(integer j=0;j<`K0;j=j+1)begin
                         data_reg[i][j] <= 'd0; 
                      end
                        valid_reg[i] <= 'd0;
                        position_reg[i] <= 'd0;
                        psum_reg[i] <= 'd0;
                    end
                end
                else begin
                    data_reg[0] <= data_in;
                    valid_reg[0] <= data_in_valid;
                    position_reg[0] <= position_di;
                    psum_reg[0] <= psum_en_di;
                    for (i = 1; i < LEN; i = i + 1)begin
                        valid_reg[i] <= valid_reg[i-1];
                        data_reg[i] <= data_reg[i-1];
                        position_reg[i] <= position_reg[i-1];
                        psum_reg[i] <= psum_reg[i-1];
                    end          
                end
            end
            assign data_out = data_reg[LEN-1];
            assign data_out_valid = valid_reg[LEN-1];
            assign position_do = position_reg[LEN-1];
            assign psum_en_do = psum_reg[LEN-1];
        end
    endgenerate
endmodule